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948f-01 MC9S08SC4 freescale semiconductor data sheet: technical data document number: MC9S08SC4 rev. 4, 6/2010 ? freescale semiconductor, inc., 2009-2010. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. MC9S08SC4 8-bit microcontroller data sheet 8-bit hcs08 central processor unit (cpu) ? up to 40 mhz hcs08 cpu (cen tral processor unit); up to 20 mhz bus frequency ? hc08 instruction set with added bgnd instruction on-chip memory ? 4 kb of flash with read/program/erase over full operating voltage and temperature ? 256 bytes of random -access memory (ram) power-saving modes ? two very low power stop modes ? reduced power wait mode clock source options ? oscillator (xosc) ? loop- control pierce oscillator; crystal or ceramic resonator range of 32 khz to 38.4 khz or 1 mhz to 16 mhz ? internal clock source (ics ) ? internal clock source module containing a frequency-locked loop (fll) controlled by internal or ex ternal reference; precision trimming of internal reference allows 0.2 % resolution and 2.0 % deviation over temperature and voltage; supports bus frequencies from 2 mhz to 20 mhz. system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1 khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points ? illegal opcode detection with reset ? illegal address detection with reset ? flash block protect ? reset on loss of clock development support ? single-wire background debug interface ? breakpoint capability to allow single breakpoint setting during in-circuit debugging peripherals ? sci ? serial communication interface ? full-duplex non-return to zero (nrz) ? lin master extended break generation ? lin slave extended break detection ? wake-up on active edge ? tpmx ? two 2-channel timer/pwm modules (tpm1 and tpm2) ? 16-bit modulus or up/down counters ? input capture, output compare, buffered edge-aligned or center-aligned pwm ? adc ? analog to digital converter ? 8-channel, 10-bit resolution ?2.5 s conversion time ? automatic co mpare function ? temperature sensor ? internal bandgap reference channel input/output ? 12 general purpose i/o pins (gpios) ? 8 interrupt pins with selectable polarity ? hysteresis and configurable pull-up device on all input pins; configurable slew rate and drive strength on all output pins. package options ? 16-tssop operating parameters ? 4.5-5.5 v operation ? c,v, m temperature ranges available, covering -40 - 125 c operation
MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 2 table of contents chapter 1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 chapter 2 pins and connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 device pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5 chapter 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .7 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . .8 3.5 esd protection and latch-up immunity . . . . . . . . . . . . .9 3.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.7 supply current characteristics . . . . . . . . . . . . . . . . . . .13 3.8 external oscillator (xosc) characteristics . . . . . . . . .16 3.9 internal clock source (ics) c haracteristics . . . . . . . . 18 3.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11.2 tpm module timing . . . . . . . . . . . . . . . . . . . . . 22 3.12 flash specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 emc performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13.1 radiated emissions . . . . . . . . . . . . . . . . . . . . . 24 chapter 4 ordering information and mechanical drawings . . . . . . . . . . 25 4.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 device numbering scheme . . . . . . . . . . . . . . . 25 4.2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 mechanical drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 3 chapter 1 device overview the MC9S08SC4 is a member of the low- cost, high-performance hcs08 family of 8-bit microcontroller units (mcus). the MC9S08SC4 uses the enhanced hcs08 core. 1.1 mcu block diagram the block diagram in figure 1-1 shows the structure of the MC9S08SC4 mcu. figure 1-1. MC9S08SC4 block diagram ptb7/extal port b ptb6/xtal ptb5/tpm1ch1 ptb4/tpm2ch1 ptb3/pib3/adp7 ptb2/pib2/adp6 port a pta1/pia1/tpm2ch0/adp1 ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 pta3/pia3/adp3 pta2/pia2/adp2 pta0/pia0/tpm1ch0/tclk/adp0 1: v dda /v refh and v ssa /v refl , are derived from v dd and v ss respectively. user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop interface module (sci) serial communications voltage rxd txd 40-mhz internal clock source (ics) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit bkgd/ms 16-bit timer/pwm module (tpm2) tclk (MC9S08SC4 = 4096 bytes) tpm2ch0 tpm2ch1 adp7-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 (MC9S08SC4 = 256 bytes) reset see note 1 notes regulator lvd 32 khz to 38.4 khz low-power oscillator 1 mhz to 16 mhz
chapter 1 device overview MC9S08SC4 mcu series data sheet, rev. 4 4 freescale semiconductor
MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 5 chapter 2 pins and connections this section describes signals that connect to package pins. it includes pinout diag rams, recommended system connections, and detailed discussions of signals. 2.1 device pin assignment the following figure shows the pin assignments for the MC9S08SC4 device. table 2-1. pin function priority pin number priority 16-pin port pin alt 1 alt 2 alt 3 alt 4 1 reset 2 bkgd ms 3 v dd 4 v ss 5 ptb7 extal 6ptb6 xtal 7 ptb5 tpm1ch1 8 ptb4 tpm2ch1 9ptb3 pib3 adp7 10 ptb2 pib2 adp6 11 ptb1 pib1 txd adp5 ptb1/pib1/txd/adp5 ptb5/tpm1ch1 ptb6/xtal ptb2/pib2/adp6 pta3/pia3/adp3 ptb4/tpm2ch1 ptb3/pib3/adp7 ptb0/pib0/rxd/adp4 v dd v ss ptb7/extal 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 bkgd/ms reset pta2/pia2/adp2 pta1/pia1/tpm2ch0/adp1 pta0/pia0/tpm1ch0/tclk/adp0 lowest highest
chapter 2 pins and connections MC9S08SC4 mcu series data sheet, rev. 4 6 freescale semiconductor 12 ptb0 pib0 rxd adp4 13 pta3 pia3 adp3 14 pta2 pia2 adp2 15 pta1 pia1 tpm2ch0 adp1 16 pta0 pia0 tpm1ch0 tclk adp0 table 2-1. pin function priority (continued) pin number priority 16-pin port pin alt 1 alt 2 alt 3 alt 4 lowest highest
MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 7 chapter 3 electrical characteristics 3.1 introduction this section contains electrical and timing specifications for the MC9S08SC4 series of microcontr ollers available at the time of publication. 3.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following cla ssification is used and the parameters are tagge d accordingly in the tables where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table 3-2 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advise d that normal precautions be taken to av oid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs ar e tied to an appropriate logic voltage level (f or instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table 3-1. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations.
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 8 freescale semiconductor 3.4 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being c ontrolled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current fo r each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. table 3-2. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +5.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value s pecified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?55 to 150 c table 3-3. thermal characteristics num c rating symbol value unit 1 ? operating temperature range (packaged) t l to t h c ct a ?40 to 85 v ?40 to 105 m ?40 to 125 maximum junction temperature ? c 2d ct jm 95 v 115 m 135 thermal resistance 1,2 single-layer board 3 d 16-pin tssop ja 130 c/w thermal resistance 1,2 four-layer board 4 d 16-pin tssop ja 87 c/w
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 9 the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 3-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 3-2 solving equation 3-1 and equation 3-2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3-3 where k is a constant pertaining to the particular pa rt. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 3-1 and equation 3-2 iteratively for any value of t a 3.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices th an on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qual ification tests are pe rformed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test qu alification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd puls es the device no longer meets the device specification. complete dc parametric and functional testing is pe rformed per the applicable device specificat ion at room temperature followed by hot temperature, unless specified othe rwise in the device specification. 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air fl ow, power dissipation of other components on the board, and board thermal resistance. 2 junction to ambient natural convection table 3-4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin ? 3 ? latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 10 freescale semiconductor 3.6 dc characteristics this section includes informatio n about power supply requiremen ts and i/o pin characteristics. table 3-5. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 charge device model (cdm) v cdm 500 ? v 3 latch-up current at t a = 125 ci lat 100 ? ma table 3-6. dc characteristics num c characteristic symbol condition min typ 1 max unit 4 ? operating voltage v dd ? 4.5 ? 5.5 v 5 c all i/o pins, 5 v, i load = ?4 ma v dd ? 1.5 ? ? p output high low-drive strength v oh 5 v, i load = ?2 ma v dd ? 0.8 ? ? v c voltage all i/o pins, 5 v, i load = ?20 ma v dd ? 1.5 ? ? p high-drive strength 5 v, i load = ?10 ma v dd ? 0.8 ? ? 6c output high current max total i oh for all ports i oht v out < v dd 0 ? ?100 ma 7 c all i/o pins 5 v, i load = 4 ma ? ? 1.5 p output low low-drive strength v ol 5 v, i load = 2 ma ? ? 0.8 c voltage all i/o pins 5 v, i load = 20 ma ? ? 1.5 v p high-drive strength 5 v, i load = 10 ma ? ? 0.8 8c output low current max total i ol for all ports i olt v out > v ss 0?100ma 9 p input high voltage; all digital inputs v ih 5v 0.65 x v dd ??v 10 p input low voltage; all digital inputs v il 5v ? ? 0.35 x v dd v 11 c input hysteresis v hys ? 0.06 x v dd ??v 12 p input leakage current (per pin) | i in | v in = v dd or v ss ?0.1 1 a 13 p hi-z (off-state) leakage current (per pin) input/output port pins | i oz | v in = v dd or v ss ,? 0.1 1 a ptb6/xtal,reset v in = v dd or v ss ?0.2 2 a 14 pull-up or pull-down 2 resistors; when enabled p i/o pins r pu ,r pd ? 173752k c reset 3 r pu 17 37 52 k
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 11 15 d dc injection current 4, 5, 6, 7 single pin limit v in > v dd 0?2ma i ic v in < v ss , 0 ? ?0.2 ma total mcu limit, includes v in > v dd 0?25ma sum of all stressed pins v in < v ss , 0 ? ?5 ma 16 d input capacitance, all pins c in ???8p f 17 d ram retention voltage v ram ??0 . 61 . 0v 18 d por re-arm voltage 8 v por ? 0.9 1.4 2.0 v 19 d por re-arm time 9 t por ?1 0?? s 20 p low-voltage detection threshold ? high range v dd falling v dd rising v lv d 1 ? 3.85 3.95 4.0 4.1 4.15 4.25 v 21 p low-voltage warning threshold ? high range 1 v dd falling v dd rising v lv w 3 ? 4.45 4.55 4.6 4.7 4.75 4.85 v 22 p low-voltage warning threshold ? high range 0 v dd falling v dd rising v lv w 2 ? 4.15 4.25 4.3 4.4 4.45 4.55 v 23 t low-voltage inhibit reset/recover hysteresis v hys ? ? 100 ? mv 24 p bandgap voltage reference 10 v bg ? 1.171.201.22 v 1 typical values are measured at 25 c. characterized, not tested. 2 when a pin interrupt is configured to detect rising edges, pull-down resistors are used in place of pull-up resistors. 3 the specified resistor value is the actual value internal to the device. the pull-up value may measure higher when measured externally on the pin. 4 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when th e mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 5 all functional non-supply pins are internally clamped to v ss and v dd . 6 input must be current limited to the val ue specified. to determine the value of th e required current-limiting resistor, calcula te resistance values for positive and negative clamp vo ltages, then use the larger of the two values. 7 the reset pin does not have a clamp diode to v dd . do not drive this pin above v dd . 8 maximum is highest voltage that por will occur. 9 simulated, not tested 10 factory trimmed at v dd = 5.0 v, temp = 25 c table 3-6. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 12 freescale semiconductor figure 3-1. typical v ol vs i ol , high drive strength figure 3-2. typical v ol vs i ol , low drive strength v ol (v) i ol (ma) 20 15 10 5 025 0 0.5 1 1.5 2 a) v dd = 5v, high drive max 1.5v@20ma 125c 25c ?40c v ol (v) i ol (ma) 4321 05 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, low drive max 1.5v@4ma
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 13 figure 3-3. typical v dd ? v oh vs i oh , high drive strength figure 3-4. typical v dd ? v oh vs i oh , low drive strength 3.7 supply current characteristics this section includes information about power supply current in various operating modes. i oh (ma) ?20 ?15 ?10 ?50 ?25 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, high drive max 1.5v@ ?20ma v dd ? v oh (v) v dd ? v oh (v) i oh (ma) ?4 ?3 ?2 ?1 0?5 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, low drive max 1.5v@ ?4ma
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 14 freescale semiconductor table 3-7. supply current characteristics num c parameter symbol v dd (v) typ 1 1 typical values are based on characterization data at 25 c. see figure 3-5 through figure 3-7 for typical curves across voltage/temperature. max 2 2 max values in this column apply for the full operating temperature range of the device unless otherwise noted. unit 1 c run supply current 3 measured at (cpu clock = 4 mhz, f bus = 2 mhz) 3 all modules except adc active, ics configured for f be, and does not include any dc loads on port pins. ri dd 51.9 2.4 ma 2 p run supply current 3 measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 54.6 5.6 ma 3 c run supply current 4 measured at (cpu clock = 32 mhz, f bus = 16 mhz) 4 all modules except adc active, ics configured for fei, and does not include any dc loads on port pins. ri dd 57.8 8.9 ma c? 4 0 c (c & m suffix) 0.71 ? a p stop3 mode 25 c (all parts) 0.93 ? 4c 5 5 stop currents are tested in production for 25 c on all parts. tests at other temperatures depend upon the part number suffix and maturity of the product. freescale may eliminate a test insertion at a particular temperature from the production test flow once sufficien t data has been collected and is approved. supply current 85 c (c suffix only) s3i dd 54 11 c 5 105 c (v suffix only) 9 30 p 5 125 c (m suffix only) 28 60 5 c ?40 c (c & m suffix) 0.70 ? a p stop2 mode 25 c (all parts) 0.89 ? c 5 supply current 85 c (c suffix only) s2i dd 53 8 c 5 105 c (v suffix only) 6 22 p 5 125 c (m suffix only) 17 41 6 c lvd adder to stop3 (lvde = lvdse = 1) s3i ddlvd 5110 165 a 7 c adder to stop3 for oscillator enabled 6 (erefsten =1) 6 values given under the following conditions: low range operation (range = 0) with a 32.768 khz crystal and low power mode (hgo = 0). s3i ddosc 55 8 a
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 15 figure 3-5. typical run i dd vs. bus frequency (v dd = 5v) figure 3-6. typical run i dd vs. temperature (v dd = 5v; f bus = 8mhz) run i dd (ma) f bus (mhz) 8 421 01 6 0 2 4 10 20 6 8 fei fbelp run i dd (ma) temperature ( c ) 85 25 0 ?40 105 0 1 2 5 125 3 4 note: ics is configured to fei.
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 16 freescale semiconductor figure 3-7. typical stop i dd vs. temperature (v dd = 5v) 3.8 external oscillator (xosc) characteristics note the MC9S08SC4 series supports a narrower low frequency external reference range than the standard ics specification. all references to range "31.25 khz to 39.0625 khz" in this section should be limited to " 32.0 khz to 38.4 khz". stop i dd (a) temperature ( c ) 85 25 0 ?40 105 0 10 20 50 125 30 40 stop2 stop3
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 17 table 3-8. oscillator electrical specifications (temperature range = ?40 to 125 c ambient) num c rating symbol min typ 1 1 typical data was characterized at 5.0 v, 25 c or is recommended value. max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) f lo 32 ? 38.4 khz high range (range = 1) fee or fbe mode 2 2 the input clock source must be divided using rdiv to within the range of 31.25 khz to 39.0625 khz. f hi 1?5mhz high range (range = 1, hgo = 1) fbelp mode f hi-hgo 1?16mhz high range (range = 1, hgo = 0) fbelp mode f hi-lp 1?8mhz 2? load capacitors c 1, c 2 see crystal or resonator manufacturer?s recommendation 3? feedback resistor r f m low range (32 khz to 100 khz) ? 10 ? high range (1 mhz to 16 mhz) ? 1 ? 4? series resistor r s k low range, low gain (range = 0, hgo = 0) ? 0 ? low range, high gain (range = 0, hgo = 1) ? 100 ? high range, low gain (range = 1, hgo = 0) ? 0 ? high range, high gain (range = 1, hgo = 1) 8 mhz ? 0 0 4 mhz ? 0 10 1 mhz ? 0 20 5t crystal start-up time 3 3 this parameter is characterized and not te sted on each device. proper pc board layout procedures must be followed to achieve specifications. this data will vary based upon the crystal manufacturer and board design. the crystal should be characterized by the crystal manufacturer. ms low range, low gain (range = 0, hgo = 0) t cstl-lp ? 200 ? low range, high gain (range = 0, hgo = 1) t cstl-hgo ? 400 ? high range, low gain (range = 1, hgo = 0) 4 4 4 mhz crystal. t csth-lp ?5? high range, high gain (range = 1, hgo = 1) 4 t csth-hgo ?15? 6t square wave input clock frequency (erefs = 0, erclken = 1) f extal fee or fbe mode 2 0.03125 ? 5 mhz fbelp mode 0 ? 40 mhz
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 18 freescale semiconductor 3.9 internal clock source (ics) characteristics table 3-9. ics frequency specifications (temperature range = ?40 to 125 c ambient) num c rating symbol mi n typical max unit 1p internal reference frequency - factory trimmed at v dd = 5 v and temperature = 25 c f int_ft ? 31.25 ? khz 2t internal reference frequency - untrimmed 1 1 trim register at default value (0x80) and ftrim control bit at default value (0x0). f int_ut 25 36 41.66 khz 3 p internal reference frequency - user trimmed f int_t 31.25 ? 39.0625 khz 4 t internal reference startup time t irefst ?? 6 s 5? dco output frequency range - untrimmed 1 value provided for reference assumes: fdco_ut = 1024 x f int_ut f dco_ut 25.6 36.86 42.66 mhz 6 d dco output frequency range - trimmed f dco_t 32 ? 40 mhz 7d resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 8d resolution of trimmed dco output frequency at fixed voltage and temperatur e (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco 9d total deviation from actual trimmed dco output frequency over voltage and temperature f dco_t ? + 0.5 ? 1.0 2.0 %f dco 10 d total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0 c to 70 c f dco_t ? 0.5 1 %f dco 11 d fll acquisition time 2 2 this specification applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll en abled (fei, fee, fbe, fbi). if a crystal/re sonator is being used as the reference, this specification assumes it is already running. t acquire ?? 1ms 12 d dco output clock long term jitter (over 2ms interval) 3 3 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injecte d into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. c jitter ?0.020.2 %f dco mcu extal xtal crystal or resonator r s c 2 r f c 1
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 19 3.10 adc characteristics figure 3-8. adc input impeda nce equivalency diagram table 3-10. adc operating conditions characteristic conditions symb min typ 1 1 typical values assume vdda = 5.0 v, temp = 25 c, fadck=1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment supply voltage absolute v dda 2 2 v dda /v refh and v ssa /v refl , are derived from v dd and v ss respectively. 2.7 ? 5.5 v ? input voltage ? v adin v refl 2 ?v refh 2 v? input capacitance ?c adin ?4.55.5pf ? input resistance ?r adin ?3 5k ? analog source resistance 10 bit mode f adck > 4mhz f adck < 4mhz r as ? ? ? ? 5 10 k external to mcu 8 bit mode (all valid f adck )? ? 1 0 adc conversion clock frequency high speed (adlpc=0) f adck 0.4 ? 8.0 mhz ? low power (adlpc=1) 0.4 ? 4.0 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 20 freescale semiconductor table 3-11. adc characteristics characteristic conditions c symb min typ 1 max unit comment supply current adlpc=1 adlsmp=1 adco=1 ?ti dda ?133? a? supply current adlpc=1 adlsmp=0 adco=1 ?ti dda ?218? a? supply current adlpc=0 adlsmp=1 adco=1 ?ti dda ?327? a? supply current adlpc=0 adlsmp=0 adco=1 ?ti dda ? 0.582 1 ma ? adc asynchronous clock source high speed (adlpc=0) p f adack 23.35mhzt adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp=0) pt adc ? 20 ? adck cycles see adc chapter in MC9S08SC4 reference manual for conversion time variances long sample (adlsmp=1) ?40? sample time short sample (adlsmp=0) pt ads ? 3.5 ? adck cycles long sample (adlsmp=1) ? 23.5 ? to t a l unadjusted error 10 bit mode p e tue ? 1.5 3.5 lsb includes quantization 8 bit mode ? 0.7 1.5 differential non-linearity 10 bit mode p dnl ? 0.5 1.0 lsb 8 bit mode ? 0.3 0.5 monotonicity and no-missing-codes guaranteed integral non-linearity 10 bit mode c inl ? 0.5 1.0 lsb 8 bit mode ? 0.3 0.5 zero-scale error 10 bit mode p e zs ? 1.5 2.5 lsb v adin = v ssa 8 bit mode ? 0.5 0.7 full-scale error 10 bit mode p e fs ? 1 1.5 lsb v adin = v dda 8 bit mode ? 0.5 0.5
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 21 3.11 ac characteristics this section describes ac timing char acteristics for each peripheral system. 3.11.1 control timing quantization error 10 bit mode d e q ?? 0.5 lsb ? 8 bit mode ? ? 0.5 input leakage error 10 bit mode d e il ? 0.2 2.5 lsb pad leakage 2 * r as 8 bit mode ? 0.1 1 temp sensor slope ?40 c? 25 c d m ? 3.266 ? mv/ c? 25 c? 125 c? 3.638 ? temp sensor voltage 25 cd v temp2 5 ? 1.396 ? v ? 1 typical values assume v dda = 5.0v, temp = 25c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 based on input pad leakage current. refer to pad electricals. table 3-12. control timing num c rating symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0v, 25 c unless otherwise stated. max unit 1d bus frequency (t cyc = 1/f bus )f bus dc ? 20 mhz 2 p internal low power oscillator period t lpo 700 975 1500 s 3d external reset pulse width 2 t extrst 100 ? ? ns 4d reset low drive 3 t rstdrv 66 x t cyc ??ns 5d pin interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 x t cyc ??ns 6c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 40 75 ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 11 35 ? ? ns table 3-11. adc characteristics characteristic conditions c symb min typ 1 max unit comment
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 22 freescale semiconductor figure 3-9. reset timing 3.11.2 tpm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. 2 this is the shortest pulse that is guarant eed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. refer to figure 3-9 . 3 when any reset is initiate d, internal circuitry drives the re set pin low for about 66 cycles of t cyc . after por reset the bus clock frequency changes to the untrimmed dco frequency (f reset = (f dco_ut )/4) because trim is reset to 0x80 and ftrim is reset to 0, and there is an extra divide-by-two because bdiv is rese t to 0:1. after other resets trim stays at the pre-reset value. 4 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 125 c. table 3-13. tpm input timing num c rating symbol min max unit 1 ? external clock frequency f text dc 1/4 f op mhz 2 ? external clock period t text 4?t cyc 3 ? external clock high time t tclkh 1.5 ? t cyc 4 ? external clock low time t tclkl 1.5 ? t cyc 5 ? input capture pulse width f icpw 1.5 ? t cyc t extrst reset pin
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 23 3.12 flash specifications this section provides details about program/erase ti mes and program-erase endura nce for the flash memory. program and erase operations do not require any special power sources ot her than the normal v dd supply. for more detailed information about program/erase op erations, see the memory section. table 3-14. flash characteristics num c characteristic symbol min typical max unit 1 ? supply voltage for program/erase v prog/erase 4.5 ? 5.5 v 2 ? supply voltage for read operation v read 4.5 ? 5.5 v 3 ? internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 ? 200 khz 4 ? internal fclk period (1/f fclk )t fcyc 5 ? 6.67 s 5 ? byte program time (random location) 2 2 these values are hardware state machine co ntrolled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t prog 9t fcyc 6 ? byte program time (burst mode) 2 t burst 4t fcyc 7 ? page erase time 2 t page 4000 t fcyc 8 ? mass erase time 2 t mass 20,000 t fcyc 9c program/erase endurance 3 t l to t h = ?40 c to +125 c t = 25 c 3 typical endurance for flash is based on the intrinsic bit cell performance. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory. n flpe 10,000 ? ? 100,000 ? ? cycles 10 c data retention 4 4 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 ? years ipg_clk t cyc external clock input capture t text t tclkh t tclkl t icpw
chapter 3 electrical characteristics MC9S08SC4 mcu series data sheet, rev. 4 24 freescale semiconductor 3.13 emc performance electromagnetic compatibility (emc) performance is highly de pendant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and charact eristics of external components as well as mcu software operation all play a significant role in emc performance. the sy stem designer should consult fr eescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifically targeted at optimizing emc performance. 3.13.1 radiated emissions microcontroller radiated rf emissions ar e measured from 150 khz to 1 ghz usi ng the tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurem ent is performed with the microcontroller installed on a custom emc evaluation board while running specialized emc test software. the radiated emissions from the microcontroller are measured in a tem cell in two pack age orientations (north and east). the maximum radiated rf emissi ons of the tested configuration in all orientations are less than or equal to the reported emissions levels. table 3-15. radiated emissions, electric field parameter symbol conditions frequency f osc /f bus level 1 (max) 1 data based on qualification test results. unit radiated emissions, electric field v re_tem v dd = 5 v t a = +25 o c package type 16-tssop 0.15 ? 50 mhz 4 mhz crystal 8 mhz bus ?7 db v 50 ? 150 mhz ?11 150 ? 500 mhz ?11 500 ? 1000 mhz ?10 iec level n ? sae level 1 ?
chapter 4 ordering information and mechanical drawings MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 25 chapter 4 ordering information and mechanical drawings 4.1 ordering information this section contains ordering information for MC9S08SC4 device. 4.1.1 device numbering scheme 4.2 package information 4.3 mechanical drawings the following pages are mechanical dr awings for the package described in table 4-2 . table 4-1. device numbering system device number 1 1 see MC9S08SC4 reference manual for a complete description of modules. included on each device. memory available packages 2 2 see ta bl e 4 - 2 for package information. flash ram s9s08sc4e0mtg 4k 256 16 tssop table 4-2. package information pin count type designator case number document no. 16 tssop tg 948f-01 98ash70247a status - s = auto qualified main memory type - 9 = flash-based core s family memory size - 4 kbytes mask set identifier - identifies mask. temperature option - c = ?40 to 85 c - v = ?40 to 105 c - m = ?40 to 125 c package designator two letter descriptor (refer to ta bl e 4 - 2 ). tape and reel suffix (optional) s 9 s08 sc 4 e0 m tg r
chapter 4 ordering information and mechanical drawings MC9S08SC4 mcu series data sheet, rev. 4 26 freescale semiconductor
chapter 4 ordering information and mechanical drawings MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 27
chapter 4 ordering information and mechanical drawings MC9S08SC4 mcu series data sheet, rev. 4 28 freescale semiconductor
chapter 5 revision history MC9S08SC4 mcu series data sheet, rev. 4 freescale semiconductor 29 chapter 5 revision history to provide the most up-to-date information, the version of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. revision number revision date description of changes 1 9/2008 ? initial release. 2 7/2009 ? incorporated editing updates. ? added c and v temperature ranges at page 1. ? updated section 3.10, ?adc characteristics ?. ? updated ta b l e 3 - 3 , ta bl e 3 - 6 , ta b l e 3 - 7 , ta bl e 3 - 9 , ta b l e 3 - 1 2 , ta bl e 3 - 1 5 and section 4.1.1, ?device numbering scheme ?. ? added actual package mechanical drawings. ? updated figure 3-5 , figure 3-6 . ? removed transient susceptibilty section. ? updated disclaimer page. 3 3/2010 ? updated tssop-16 package diagram, clarif ied ics deviation, sci lin features at page 1. ? updated ta bl e 3 - 6 , ta bl e 3 - 7 , ta bl e 3 - 9 , ta bl e 3 - 1 2 , ta b l e 4 - 1 . ? updated figure 3-5 and figure 3-7 . 4 6/2010 ? document changed from advance information to technical data ? updated footnotes in ta b l e 3 - 7 ? updated figure 3-5
chapter 5 revision history MC9S08SC4 mcu series data sheet, rev. 4 30 freescale semiconductor
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